U.S. Patent Application Publication No. 2007/0108371 discloses a PMOS pixel structure in which a p-type buried storage layer is arranged under an n-type pinning layer formed on a surface, and an n-type well is arranged under the p-type buried storage layer. The pinning layer in U.S. Patent Application Publication No. 2007/0108371 is connected to an n-type isolation implant which extends under and beside an STI (Shallow Trench Isolation) region as an element isolation region. With this structure, holes, which are generated by and stored in the buried storage layer, are transferred to a floating diffusion via a transfer gate and are read out.
In the PMOS pixel structure described in U.S. Patent Application Publication No. 2007/0108371, the cathode of a photodiode is formed by the n-type well. However, the present invention adopts an approach which forms the cathode of a photodiode by an n-type buried layer. Note that a channel stopper region which covers the lower portion of an element isolation region is formed in a shallow region, while the buried layer is formed in a deep region. The channel stopper region has a boundary regulation which largely influences miniaturization, while the buried layer should give a broadly distributed potential barrier. The present invention has been made in consideration of such difference between the channel stopper region and buried layer.